1. Field of the Invention
The invention relates to a method for testing through-silicon-via (hereinafter abbreviated as TSV) structures, and more particularly, to a method for testing electrical continuity of TSV structures.
2. Description of the Prior Art
With progress in semiconductor manufacturing technology, a multitude of chips may now be integrated into one single package. And in a single package, the connection between chips is realized by TSV structures.
Conventionally, a TSV structure is formed by deep etching into the wafer or the substrate, and filling the resulting hole with a liner and a conductive filling layer. Then, the wafer is thinned from its backside, until the conductive filling layer is exposed, and a backside metal and bumps are deposited on the thinned backside for electrical contact. It is well-known that the TSV structures are not functional before forming the backside metal and the bumps. Therefore, it is extremely difficult to determine whether the TSV structure is defective or not by the conventional inline electrical testing before completing the abovementioned steps. Accordingly, throughput, efficiency, and cost of the semiconductor fabrication process are adversely influenced.